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root root root root root root root cross-nvptx-gcc10-10.4.0+git2794-150000.1.9.1.src.rpm cross-nvptx-newlib-devel cross-nvptx-newlib10-devel cross-nvptx-newlib10-devel(x86-64)
rpmlib(CompressedFileNames) rpmlib(FileDigests) rpmlib(PartialHardlinkSets) rpmlib(PayloadFilesHavePrefix) 3.0.4-1 4.6.0-1 4.0.4-1 4.0-1 cross-nvptx-newlib-devel 4.14.1 b@b8bO` @`i@`@`!@``x*`e`[)`?z@`@_ǁ_@__^@_@_@__]@_ _D@_C_*@_ @_c^ ^^ ^@^@^`^^@^H^@^^^}^y@^t@^s^^r
@^ku^f/^b;@^\@^U @^O@^K^K^C^AE^;^;^:@^!]QT]QTrguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com schwab@suse.de rguenther@suse.com rguenther@suse.com schwab@suse.de rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com lnussel@suse.de rguenther@suse.com matthewtrescott@gmail.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com guillaume.gardet@opensuse.org rguenther@suse.com matwey.kornilov@gmail.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com rguenther@suse.com mliska@suse.cz mliska@suse.cz rguenther@suse.com schwab@suse.de mliska@suse.cz mliska@suse.cz mliska@suse.cz mliska@suse.cz mliska@suse.cz mliska@suse.cz - Update to GCC 10.4 release (80c8c5b8f69bcd2dd168933fe6a), git2794
* includes remaining regression fixes from the branch - Update to gcc-10 branch head (f9982b5a81a151663c76ba0a3), git2389
- Add gcc10-PIE, similar to gcc-PIE but affecting gcc10 [bsc#1195628]
- Remove sys/rseq.h from include-fixed - Put libstdc++6-pp Requires on the shared library and drop
to Recoomends. - Properly adjust GPL-3.0 WITH GCC-exception-3.1 to
GPL-3.0-or-later WITH GCC-exception-3.1 - Remove bits/unistd_ext.h from include-fixed - Update to gcc-10 branch head (048117e16c77f82598fca9af5), git1893
* Removes cyclades header use from libsanitizer. [boo#1188076] - Force using llvm11 for amdgcn offloading since llvm12 doesn't
yet work. - Fix value of %slibdir64 for usrmerge - Update to GCC 10.3.0 release (63fa67847628e5f358e7e2e7e), git1587
- Disable nvptx offloading for aarch64 again since it doesn't work - Update to gcc-10 branch head (892024d4af83b258801ff7484), git1574
* Includes GCC 10.3 RC1 - Update to gcc-10 branch head (592388d4f6e8a6adb470428fe), git1450 - Update to gcc-10 branch head (85977f624a34eac309f9d77a5), git1331
* Includes fix for [bsc#1182016]
- The 32bit nvptx libgomp plugin is no longer built, do not attempt
to package it. - Remove include-fixed/pthread.h
- Change GCC exception licenses to SPDX format - Update to gcc-10 branch head (e563687cf9d3d1278f45aaebd), git1030
* Includes fix for firefox build [gcc#97918] - Do not specify alternate offload compiler location at
configure time.
- Update README.First-for.SuSE.packagers
- Install offload compilers for gcc10-testresults build - Enable fortran for offload compilers. - Add gcc10-amdgcn-llvm-as.patch to fix build of amdgcn offload
compiler with llvm11. - Update to gcc-10 branch head (98ba03ffe0b9f37b4916ce6238), git958.
* Includes fix for memcpy miscompilation on aarch64.
[bsc#1178624, bsc#1178577] - Fix 32bit libgnat.so link. [bsc#1178675] - prepare usrmerge: Install libgcc_s into %_libdir. ABI wise it
stays /%lib. (boo#1029961) - Update to gcc-10 branch head (a78cd759754c92cecbf235ac9b), git872. - Build complete set of multilibs for arm-none target [bsc#1106014]
* Fixes inadvertant mixture of ARM and Thumb instructions in linker output - Update to gcc-10 branch head (c0746a1beb1ba073c7981eb09f), git583.
* Fixes ABI breakage for as-base CDTORs of final classes. [gcc#95428] - Update to gcc-10 branch head (d523b5201cce1796717a8ca669), git580.
* Includes gcc10-streamer-backports1.patch and
gcc10-streamer-backports2.patch.
* Includes fixes for LTO ICE [bsc#1175168] and aarc64 128bit
CAS miscompilation [bsc#1174753]. - Update to gcc-10 branch head (dda1e9d08434def88ed86557d0), git501.
* Includes fix for AARCH64 kernel build failure. [bsc#1174817]
* Includes aarch64 SLS mitigation changes. [bsc#1172798, CVE-2020-13844]
- Add gcc10-streamer-backports1.patch and gcc10-streamer-backports2.patch.
- Enable x86 CET runtime for SLES15 and Leap15 also.
- Do not enable the now deprecated HSA offloading capability. - Update to gcc-10 branch head (c0438ced53bcf57e4ebb1c38c), git465.
* Includes GCC 10.2 release. [bsc#1173972] [jsc#ECO-2373]
* Picks up fixes for C++20 coroutines support. [jsc#SLE-12297]
* Picks up fix for a recent chromium build fail.
- Build x86 CET enabled runtime for Factory.
- Disable GCN offloading for SLE12 and SLE15 GA. - Update to gcc-10 branch head (12e1a54b06777db74ce375496), git355.
* Includes fix for non-reproducible builds with LTO [bsc#1172846]. - Enable nvptx support for aarch64 - Update to gcc-10 branch head (c91e43e9363bd119a695d6450), git290.
* Includes fix for PR95719, fixing LibreOffice. - Enable c++ for arm-none-eabi - Update to gcc-10 branch head (b0461f44076c26ced5526e4fd6), git68.
- Add gcc10-foffload-default.patch to make offloading ignore
offload targets that have not been installed both at compile
and runtime (for the libgomp plugin part). - Update to gcc-10 branch head (dd38686d9c810cecbaa80bb82e), git40.
* Includes GCC 10.1 release. - Update to gcc-10 branch head (2aaa1dc3c87372fd55c1c33aa7a), git5.
* Includes first release candidate for GCC 10.1.
* Includes gcc10-pr94734.patch - Update to master head (3685c5adf5c0b30268cb8f95c89e4), git176017.
- Add gcc10-pr94734.patch - Update to master head (b835645c7a51b7e99092abe61d677), git175845.
- Drop to 4 jobs as constraint for s390x. - Update to master head (effcb4181e143bc390286a489ff84), git175831.
- Package arm_cde.h and arm_mve_types.h for arm.
- Alter _constraints to also constrain jobs.
- Add libzstd-devel BuildRequires to cross compiler specs.
- Switch to release checking builds. - Update to master head (2dc9294c3c7c81a6d5e1d4dedf58f), git175805. - Update to master head (13e41d8b9d3d7598c72c38acc86a3), git175688. - Update to master head (c72a1b6f8b26de37d1a922a8af143), git175641. - Update to master head (038769535a8cbdd3dd3e100bde314), git175499. - Update to master head (75c24a08d697d6442fe6c26142f05), git175422. - Update to master head (7d4549b2cd209eb621453ce13be7f), git175366. - Update to master head (c7e9019681857b329bbe4c1e7ec8d), git175348.
- Package arm_mve.h for arm. - Update to master head (4e3d3e40726e1b68bf52fa205c68495124ea60b8).
- libgphobos and libgdruntime SONAME versions were reset to 1. - Update to master head (3604480a6fe493c51d6ebd53d9b1abeebbbb828f). - Update embedded newlib to newlib-3.3.0.tar.xz, drop old
newlib-3.1.0.tar.xz
- Enable support for amdgcn-amdhsa OpenMP/OpenACC offloading. - Update to master head (655e5c29ae4080666154b3e10ac81116a1b7a638).
- Re-add gcc9-reproducible-builds.patch and
gcc9-reproducible-builds-buildid-for-checksum.patch. - Update to master head (778a77357cad11e8dd4c810544330af0fbe843b1).
* Includes fix for binutils version parsing [gcc#93965] - Add libstdc++6-pp provides and conflicts to avoid file conflicts
with same minor version of libstdc++6-pp from gcc9. - Disable zstd use for SLES15 and older. - Bump to rfa1160f6e50500aa38162fefb43bfb10c25e0363. - Bump to r33351ff9faa21c4c1af377d661a52ac0ce366db3. - Adjust installed headers for arm and aarch64, enable link-mutex
for riscv64. - Don't remove go tool buildid, needed for bootstrapping go
- Increase disk constraint - Bump to rc940105cc17111be98d8d42ba48a413b0e63aebe. - Bump libtool version of libgo. - Bump to r269e8130b77065452698ab97e5da77d132d00276. - Bump to r507de5ee23efdc8a16d6b0b6488e118055c711cd. - Add lto-dump to cross packages. - New package, inherits from gcc9
* gcc-add-defaultsspec.diff, add the ability to provide a specs
file that is read by default
* tls-no-direct.diff, avoid direct %fs references on x86 to not
slow down Xen
* gcc43-no-unwind-tables.diff, do not produce unwind tables for
CRT files
* gcc41-ppc32-retaddr.patch, fix expansion of __builtin_return_addr
for ppc, just a testcase
* gcc44-textdomain.patch, make translation files version specific
and adjust textdomain to find them
* gcc44-rename-info-files.patch, fix cross-references in info files
when renaming them to be version specific
* gcc48-libstdc++-api-reference.patch, fix link in the installed
libstdc++ html documentation
* gcc48-remove-mpfr-2.4.0-requirement.patch, make GCC work with
earlier mpfr versions on old products
* gcc5-no-return-gcc43-workaround.patch, make build work with
host gcc 4.3
* gcc7-remove-Wexpansion-to-defined-from-Wextra.patch, removes
new warning from -Wextra
* gcc7-avoid-fixinc-error.diff goat08 1658142889
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ 10.4.0+git2794-150000.1.9.1 10.4.0+git2794-150000.1.9.1 10.4.0+git2794-150000.1.9.1 nvptx-none include _ansi.h _newlib_version.h _syslist.h alloca.h ar.h argz.h assert.h bits complex.h cpio.h ctype.h devctl.h dirent.h elf.h envlock.h envz.h errno.h fastmath.h fcntl.h fenv.h fnmatch.h getopt.h glob.h grp.h iconv.h ieeefp.h inttypes.h langinfo.h libgen.h limits.h locale.h machine _arc4random.h _default_types.h _endian.h _time.h _types.h ansi.h endian.h fastmath.h ieeefp.h malloc.h param.h setjmp-dj.h setjmp.h stdlib.h termios.h time.h types.h malloc.h math.h memory.h ndbm.h newlib.h paths.h pthread.h pwd.h reent.h regdef.h regex.h rpc sched.h search.h setjmp.h signal.h spawn.h ssp ssp.h stdio.h stdlib.h string.h strings.h unistd.h wchar.h stdatomic.h stdint.h stdio.h stdio_ext.h stdlib.h string.h strings.h sys _default_fcntl.h _intsup.h _locale.h _pthreadtypes.h _sigset.h _stdint.h _timespec.h _timeval.h _types.h cdefs.h config.h custom_file.h dir.h dirent.h errno.h fcntl.h features.h fenv.h file.h iconvnls.h lock.h param.h queue.h reent.h resource.h sched.h select.h signal.h stat.h stdio.h string.h syslimits.h time.h timeb.h times.h timespec.h tree.h types.h unistd.h utime.h wait.h tar.h termios.h tgmath.h threads.h time.h unctrl.h unistd.h utime.h utmp.h wchar.h wctype.h wordexp.h lib libc.a libg.a libm.a mgomp libc.a libg.a libm.a /usr/ /usr/nvptx-none/ /usr/nvptx-none/include/ /usr/nvptx-none/include/machine/ /usr/nvptx-none/include/ssp/ /usr/nvptx-none/include/sys/ /usr/nvptx-none/lib/ /usr/nvptx-none/lib/mgomp/ -fmessage-length=0 -grecord-gcc-switches -O2 -Wall -D_FORTIFY_SOURCE=2 -fstack-protector-strong -funwind-tables -fasynchronous-unwind-tables -fstack-clash-protection -g obs://build.suse.de/SUSE:Maintenance:25109/SUSE_SLE-15_Update/4197c1cd44b89617e1e91622ddfda226-cross-nvptx-gcc10.SUSE_SLE-15_Update drpm x86_64-suse-linux directory C source, ASCII text C source, UTF-8 Unicode text ASCII text current ar archive 5R
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ۯ< \ٔ})k{7] f#ט42E?]B@"4 Q&0 0 0 644 predpred15
mov.f64 %r70,0d7ff0000000000000;
fma.rn.f64 %r28,%r70,0d0000000000000000,%r70;
.loc 1 129 9
st.f64 [%r42],%r280 0 0 644 predpredpred52 5
setp.neu.f32 %r51,%r47,0f00000000;
@ %r51 bra $L2;
.loc 1 52 18
setp.gt.f32 %r52,%r50,0f3f800000;
@ %r52 bra $L3;
$L2:
.loc 1 55 5
mul.f32 %r32,%r47,%r47;
.loc 1 56 4
neg.f32 %r53,%r50;
.loc 1 56 11
mov.f32 %r55,0f3f800000;
sub.f32 %r54,%r55,%r32;
.loc 1 56 4
fma.rn.f32 %r33,%r53,%r50,%r54;
.loc 1 57 5
setp.eq.f32 %r56,%r33,0f00000000;
@ %r56 bra $L3;
.loc 1 60 13
add.f32 %r59,%r4716
mov.f32 %r70,0f7f800000;
fma.rn.f32 %r28,%r70,0f00000000,%r70;
.loc 1 78 9
st.f32 [%r42],%r28predpred16
mov.f64 %r70,0d7ff0000000000000;
fma.rn.f64 %r28,%r70,0d0000000000000000,%r70;
.loc 1 75 9
st.f64 [%r42],%r280 0 0 644 mov.f64 %r62,0d7ff0000000000000;
fma.rn.f64 %r29,%r62,0d0000000000000000,%r62;
.loc 1 86 10
st.f64 [%r40],%r290 0 0 644 mov.f32 %r62,0f7f800000;
fma.rn.f32 %r29,%r62,0f00000000,%r62;
.loc 1 53 10
st.f32 [%r40],%r290 0 0 644 4485mov.f64 %r62,0d7ff0000000000000;
fma.rn.f64 %r29,%r62,0d0000000000000000,%r62;
.loc 1 51 10
st.f64 [%r40],%r29
lib_a-e_acos.o/ 0 0 0 644 0 0 0 644 predpred15
mov.f64 %r70,0d7ff0000000000000;
fma.rn.f64 %r28,%r70,0d0000000000000000,%r70;
.loc 1 129 9
st.f64 [%r42],%r280 0 0 644 predpredpred52 5
setp.neu.f32 %r51,%r47,0f00000000;
@ %r51 bra $L2;
.loc 1 52 18
setp.gt.f32 %r52,%r50,0f3f800000;
@ %r52 bra $L3;
$L2:
.loc 1 55 5
mul.f32 %r32,%r47,%r47;
.loc 1 56 4
neg.f32 %r53,%r50;
.loc 1 56 11
mov.f32 %r55,0f3f800000;
sub.f32 %r54,%r55,%r32;
.loc 1 56 4
fma.rn.f32 %r33,%r53,%r50,%r54;
.loc 1 57 5
setp.eq.f32 %r56,%r33,0f00000000;
@ %r56 bra $L3;
.loc 1 60 13
add.f32 %r59,%r4716
mov.f32 %r70,0f7f800000;
fma.rn.f32 %r28,%r70,0f00000000,%r70;
.loc 1 78 9
st.f32 [%r42],%r280 0 0 644 predpred16
mov.f64 %r70,0d7ff0000000000000;
fma.rn.f64 %r28,%r70,0d0000000000000000,%r70;
.loc 1 75 9
st.f64 [%r42],%r280 0 0 644 mov.f64 %r62,0d7ff0000000000000;
fma.rn.f64 %r29,%r62,0d0000000000000000,%r62;
.loc 1 86 10
st.f64 [%r40],%r29
lib_a-ctanf.o/ 0 0 0 644 mov.f32 %r62,0f7f800000;
fma.rn.f32 %r29,%r62,0f00000000,%r62;
.loc 1 53 10
st.f32 [%r40],%r29mov.f64 %r62,0d7ff0000000000000;
fma.rn.f64 %r29,%r62,0d0000000000000000,%r62;
.loc 1 51 10
st.f64 [%r40],%r29.loc 1 429 3
lib_a-efgcvt.o/ 0 0 0 644 f.loc 1 356 399;
.reg .f64 %r104;
.reg .f64 %r125;
.reg .u32 %r130;
.reg .u32 %r133;
.reg .u32 %r135;
.reg .f64mov.u32 %r255,%r251;
mov.u32 %r251,%r34755,%r251;
mov.u32 %r251,%r347;4999,%r230;
mov.b64 %r356,%r9999_sspredu64predpred %r413;
.reg .u32pred %r424;
.reg .u32pred %r444;
.reg .u32 %r445;
.reg .u64 %r447;
.reg .u32 %r448;
.reg .u64 %r449;
.reg .u64 %r451;
.reg .u32 %r452;
.reg .pred %r453;
.reg .u3216u32u32pred64predpred %r615;
.reg .u32u16 %r695;
.reg .u16 %r696;
.reg .u16pred %r707;
.reg .predpred.u32 %r253,[%r268];.u32 %r254,[%r268];
add.u64 %r268,%r268,4;
.loc 1 921 13cvt.u16.u32 %r393,%r254;
cvt.s64.s16 %r158,%r393;
.loc 1 923 8
mov.u64 %r55,%r158;
bra $L59;
$L61:
.loc 1 921 13
cvt.s64.s32 %r158,%r254;
.loc 1 923 8
mov.u64 %r55.loc 1 1163 11u64 %r426;
.reg .u64 %r428;
.reg .u16u64 %r473;
.reg .u32predpredu32predpred %r540;
.reg .u16u32 %r544;
.reg .predu32 %r567;
.reg .pred %r568;
.reg .u64 %r569;
.reg .u64u32 %r586;
.reg .u16u64 %r589;
.reg .u64 %r590;
.reg .u32u16 %r636;
.reg .u16 %r637;
.reg .u32 %r638;
.reg .pred643264predu32 %r747;
.reg .u32 %r749;
.reg .u32 %r750;
.reg .u16 %r751;
.reg .u16 %r752;
.reg .u16 %r753;
.reg .u32 %r754;
.reg .u16 %r755;
.reg .predu32 %r779;
.reg .u16 %r780;
.reg .pred %r781;
.reg .u64 %r784;
.reg .u32 %r785;
.reg .u6416u32predpred %r833;
.reg .pred %r834;
.reg .pred %r836;
.reg .u32 %r841;
.reg .pred %r842;
.reg .u16pred %r953;
.reg .predpred %r962;
.reg .u64 %r963;
.reg .u64u32 %r983;
.reg .pred %r984;
.reg .pred %r985;
.reg .pred %r986;
.reg .u64 %r988;
.reg .pred %r989;
.reg .u32 %r994;
.reg .pred %r995;
.reg .pred %r996;
.reg .pred %r998;
.reg .u32 %r1003;
.reg .predpredpred %r1056;
.reg .u32pred %r1065;
.reg .u64 %r1067;
.reg .pred %r1068;
.reg .u32 %r1073;
.reg .pred %r1074;
.reg .predu32pred %r1123;
.reg .pred %r1125;
.reg .u32 %r1130;
.reg .pred %r1131;
.reg .u64 %r1132;
.reg .predu32 %r1172;
.reg .u32 %r1177;
.reg .pred %r1178;
.reg .u64 %r1179;
.reg .pred %r1180;
.reg .u64pred %r1188;
.reg .u32 %r1190;
.reg .predu16 %r1214;
.reg .u32u32 %r1221;
.reg .u64 %r1229;
.reg .pred %r1231;
.reg .u64 %r1232;
.reg .u32 %r1233;
.reg .pred %r1234;
.reg .u32 %r1237;
.reg .u32 %r1238;
.reg .u64 %r1245;
.reg .u64 %r1246;
.reg .u64 %r1247;
.reg .u32 %r1248;
.reg .predu16 %r1258;
.reg .u3273 12
ld.u16 %r430,[%r413+16];
and.b16 %r429,%r430,128;
setp.eq.u16 %r431,%r429,0;
@ %r431 bra $L2;
.loc 1 873 33
ld.u64 %r432,[%r413+24];64412.loc 1 1192 13
mov.u64 %r415,%r388;
bra $L63;
$L65:.loc 1 1192 13
mov.u64 %r415movmovmovmovmov.u64 %r415,%r400;
bra $L127;
$L129:
cvt.u64.u32 %r254,%r401;
mov1003,[%value_in];
}
setp.ne.u32 %r1004,%r10031
/1580 0 0 0 644 54833predu16 %r612;
.reg .predpred %r629;
.reg .u64 %r632;
.reg .u64u64 %r652;
.reg .u32 %r653;
.reg .pred %r654;
.reg .u32 %r656;
.reg .u32u32u32 %r673;
.reg .pred %r676;
.reg .pred %r679;
.reg .predu32 %r699;
.reg .pred %r700;
.reg .predu32 %r713;
.reg .pred %r714;
.reg .u64pred %r754;
.reg .u64pred %r793;
.reg .u32 %r794;
.reg .predu32predu16 %r828;
.reg .u32u64 %r864;
.reg .pred %r865;
.reg .predu64 %r877;
.reg .pred %r878;
.reg .u32predpred %r951;
.reg .u64 %r953;
.reg .pred %r954;
.reg .u32 %r959;
.reg .predpred %r971;
.reg .predu32 %r1031;
.reg .u32 %r1032;
.reg .pred %r1033;
.reg .u64 %r1035;
.reg .u32 %r1036;
.reg .pred %r1037;
.reg .u32 %r1042;
.reg .pred %r1043;
.reg .pred %r1044;
.reg .predpredu64predu64 %r1108;
.reg .pred %r1109;
.reg .u32 %r1110;
.reg .pred %r1111;
.reg .u64 %r1113;
.reg .u32u32pred %r1176;
.reg .u32 %r1181;
.reg .pred %r1182;
.reg .u32 %r1183;
.reg .pred %r1184;
.reg .u64 %r1185;
.reg .u64 %r1186;
.reg .predpredpredpred %r1238;
.reg .u32 %r1243;
.reg .predpred %r1248;
.reg .u32 %r1253;
.reg .predpred %r1264;
.reg .u64 %r1267;
.reg .pred %r1268;
.reg .u64u32 %r1284;
.reg .pred %r1285;
.reg .u32 %r1288;
.reg .u32 %r1295;
.reg .u64 %r1299;
.reg .pred %r1300;
.reg .predu32.u32 %r428,[%r443];[%frame],%r428;
$L82:
.loc 1 915 10
mov.u32 %r569,0;
st.u32 [%frame+4],%r569;
.loc 1 917 9
st.u32 [%frame+392],%r569;
.loc 1 918 4.u32 %r429,[%r443];
add.u64 %r443,%r443,4;
.loc 1 921 13
and.b32 %r576,%r283,64;88;
cvt.u16.u32 %r578,%r429;
cvt.s64.s16 %r288,%r578;
.loc 1 923 8
mov.u64 %r61,%r288;
bra $L86;
$L88:
.loc 1 921 13
cvt.s64.s32 %r288,%r429;
.loc 1 923 8
mov.u64 %r61997,%r996,0;
@ %r997 bra $L173;
.loc 1 1458 7
ld.u32 %r177,[%frame+376];
.loc 1 1521 3
ld.u64 %r406,[%frame+360];
.loc 1 1457 7
mov.u64 %r291,%r1323;
$L201:
.loc 1 1458 7
add.u32 %r80,%r177,-1;
setp.le.s32 %r998,%r80,0;
@ %r998 bra $L194;
ld.u32 %r416,[%frame+352];
setp.le.s32 %r999,%r80,16;
@ ! %r999 0 0 0 644 4007predu16 %r292;
.reg .u32u16 %r357;
.reg .u16 %r358;
.reg .u16u64 %r363;
.reg .u64 %r365;
.reg .predpred32u32predpred %r421;
.reg .u32predpredpredpredu32 %r473;
.reg .u32predu64 %r501;
.reg .u32 %r502;
.reg .u64 %r503;
.reg .u64pred %r533;
.reg .u16 %r534;
.reg .u32u32 %r543;
.reg .u32u16u16 %r563;
.reg .u16u64u64 %r593;
.reg .u64predpredpredpredu32predpred %r770;
.reg .pred %r772;
.reg .u64 %r773;
.reg .u64setp.eq.u64 %r285,%r281,0;
@ %r285 bra $L2;
ld.u32 %r286,[%r281+80];
setp.ne.u32 %r287,%r286,0;
@ %r28781ld.u32 %r266,[%r284]ld.u32 %r268,[%r284];
.loc 1 921 13
and.b32 %r445,%r111,64;
setp.eq.u32 %r446,%r445,0;
@ %r446 bra $L67;
cvt.u16.u32 %r447,%r268;
cvt.s64.s16 %r164,%r447;
.loc 1 923 8
mov.u64 %r61,%r164;
.loc 1 921 13
mov.u64 %r284,%r267;
bra $L65;
$L67:
cvt.s64.s32 %r164,%r268movmov.loc 1 1163 11movmovmov.u64 %r284,%r263;
bra $L99;
$L101:
cvt.u64.u32 %r164,%r264;
mov80u64predu32 %r492;
.reg .u16u64 %r498;
.reg .u32u32predu32predu32u32 %r582;
.reg .pred %r583;
.reg .u32 %r584;
.reg .u64 %r585;
.reg .f6432u16 %r612;
.reg .predu32 %r622;
.reg .u64 %r630;
.reg .u32u32 %r637;
.reg .predu16 %r648;
.reg .u16 %r649;
.reg .u32 %r650;
.reg .u16pred %r666;
.reg .u16 %r668;
.reg .u16 %r669;
.reg .u32 %r670;
.reg .predpred %r716;
.reg .u32pred %r723;
.reg .u64pred64pred32pred %r762;
.reg .u16u32 %r779;
.reg .u16 %r780;
.reg .predu16 %r786;
.reg .u16 %r788;
.reg .u32 %r790;
.reg .predu32 %r796;
.reg .u16 %r798;
.reg .u16 %r799;
.reg .u16 %r801;
.reg .u16 %r802;
.reg .u32predpredu64 %r851;
.reg .predu32 %r869;
.reg .pred %r870;
.reg .u64u32 %r879;
.reg .predpred %r894;
.reg .u64predpred %r914;
.reg .u64 %r916;
.reg .predu64u32 %r959;
.reg .pred %r960;
.reg .u32 %r965;
.reg .pred %r966;
.reg .predu64 %r988;
.reg .u64u32 %r998;
.reg .pred %r999;
.reg .u32predpredu64 %r1157;
.reg .predpredpredpred %r1203;
.reg .u64 %r1204;
.reg .predu32u16 %r1282;
.reg .u16 %r1283;
.reg .u32 %r1284;
.reg .u16 %r1285;
.reg .pred %r1286;
.reg .predpred.loc 1 1192 13
mov.u64 %r421,%r394;
bra $L67;
$L69:
cvt.s64.s32 %r259,%r395;
.loc 1 1194 8
mov.u64 %r58,%r259;
.loc 1 1192 13
mov.u64 %r421movmovmovmovmov.u64 %r421,%r406;
bra $L131;
$L133:
cvt.u64.u32 %r259,%r407;
mov1000,%r254,1;
.loc 1 1715 23
setp.ne.u32 %r1001,%r1000,0;
@ %r10011002,[%frame+176];
add.u32 %r389,%r1002predf64u64 %r648;
.reg .u64u32 %r653;
.reg .predu32predu32u16predu32pred %r772;
.reg .u64 %r773;
.reg .u64 %r774;
.reg .u32 %r775;
.reg .pred %r776;
.reg .u64 %r777;
.reg .u64predpredpred %r803;
.reg .u64u64 %r833;
.reg .u32 %r834;
.reg .u64 %r836;
.reg .u32 %r837;
.reg .pred %r838;
.reg .u32 %r839;
.reg .pred %r840;
.reg .u32 %r841;
.reg .pred %r842;
.reg .u16u32 %r845;
.reg .pred %r846;
.reg .u32 %r847;
.reg .pred %r848;
.reg .u32 %r849;
.reg .pred %r850;
.reg .u16u32 %r876;
.reg .u32u32u32 %r903;
.reg .pred %r906;
.reg .u64 %r908;
.reg .u64 %r910;
.reg .u64u32 %r954;
.reg .predu64 %r977;
.reg .pred %r978;
.reg .u32 %r983;
.reg .predpredu64 %r1008;
.reg .pred64predpredpred %r1088;
.reg .u64 %r1090;
.reg .u32u64u32predpred %r1199;
.reg .u32 %r1204;
.reg .pred %r1205;
.reg .predpred %r1248;
.reg .pred %r1249;
.reg .pred %r1250;
.reg .u64 %r1252;
.reg .pred %r1253;
.reg .u32 %r1258;
.reg .predpred %r1271;
.reg .u32 %r1276;
.reg .pred %r1277;
.reg .u64 %r1279;
.reg .pred %r1280;
.reg .u32 %r1285;
.reg .pred %r1286;
.reg .u32 %r1287;
.reg .predu32 %r1308;
.reg .pred %r1309;
.reg .u32 %r1310;
.reg .pred %r1311;
.reg .u32 %r1312;
.reg .pred %r1313;
.reg .u32 %r1318;
.reg .pred %r1319;
.reg .u64 %r1322;
.reg .pred %r1323;
.reg .u64 %r1327;
.reg .u32 %r1328;
.reg .pred %r1330;
.reg .u16 %r1333;
.reg .u16 %r1334;
.reg .pred %r1335;
.reg .u64 %r1338;
.reg .u32 %r1339;
.reg .pred %r1340;
.reg .u32 %r1343;
.reg .u32 %r1350;
.reg .u64 %r1354;
.reg .pred %r1355;
.reg .pred %r1356;
.reg .pred %r1357;
.reg .pred %r1358;
.reg .u32 %r1360;
.reg .u32mov.u64 %r455,%ar0;
mov.u64 %r456,%ar1;
mov.u64 %r457,%ar2;
mov.u64 %r458,%ar3;
.loc 1 424 6
mov.u32 %r460,0;
st.u32 [%frame+12881300],%r464;
.loc 1 591 2
setp.eq.u64 %r465,%r455,0;
@ %r465 bra $L25;
ld.u32 %r466,[%r455+80];25r45.u32 %r443,[%r458];[%frame],%r443;
$L88:
.loc 1 915 10
mov.u32 %r624,0;
st.u32 [%frame+4],%r624;
.loc 1 917 9
st.u32 [%frame+1304],%r624;
.loc 1 918 4.u32 %r444,[%r458];
add.u64 %r458,%r458,4;
.loc 1 921 13
and.b32 %r631,%r287,6494;
cvt.u16.u32 %r633,%r444;
cvt.s64.s16 %r294,%r633;
.loc 1 923 8
mov.u64 %r64,%r294;
bra $L92;
$L94:
.loc 1 921 13
cvt.s64.s32 %r294,%r444;
.loc 1 923 8
mov.u64 %r644.loc 1 356 3.loc 1 429 3lib_a-efgcvt.o/ 0 0 0 644 .loc 1 356 399;
.reg .f64 %r104;
.reg .f64 %r125;
.reg .u32 %r130;
.reg .u32 %r133;
.reg .u32 %r135;
.reg .f64mov.u32 %r255,%r251;
mov.u32 %r251,%r34755,%r251;
mov.u32 %r251,%r347;4999,%r230;
mov.b64 %r356,%r9999
/1501 0 0 0 644 5133sspredu64predpred %r413;
.reg .u32pred %r424;
.reg .u32pred %r444;
.reg .u32 %r445;
.reg .u64 %r447;
.reg .u32 %r448;
.reg .u64 %r449;
.reg .u64 %r451;
.reg .u32 %r452;
.reg .pred %r453;
.reg .u3216u32u32pred64predpred %r615;
.reg .u32u16 %r695;
.reg .u16 %r696;
.reg .u16pred %r707;
.reg .predpred.u32 %r253,[%r268];.u32 %r254,[%r268];
add.u64 %r268,%r268,4;
.loc 1 921 13cvt.u16.u32 %r393,%r254;
cvt.s64.s16 %r158,%r393;
.loc 1 923 8
mov.u64 %r55,%r158;
bra $L59;
$L61:
.loc 1 921 13
cvt.s64.s32 %r158,%r254;
.loc 1 923 8
mov.u64 %r55.loc 1 1163 11u64 %r426;
.reg .u64 %r428;
.reg .u16u64 %r473;
.reg .u32predpredu32predpred %r540;
.reg .u16u32 %r544;
.reg .predu32 %r567;
.reg .pred %r568;
.reg .u64 %r569;
.reg .u64u32 %r586;
.reg .u16u64 %r589;
.reg .u64 %r590;
.reg .u32u16 %r636;
.reg .u16 %r637;
.reg .u32 %r638;
.reg .pred643264predu32 %r747;
.reg .u32 %r749;
.reg .u32 %r750;
.reg .u16 %r751;
.reg .u16 %r752;
.reg .u16 %r753;
.reg .u32 %r754;
.reg .u16 %r755;
.reg .predu32 %r779;
.reg .u16 %r780;
.reg .pred %r781;
.reg .u64 %r784;
.reg .u32 %r785;
.reg .u6416u32predpred %r833;
.reg .pred %r834;
.reg .pred %r836;
.reg .u32 %r841;
.reg .pred %r842;
.reg .u16pred %r953;
.reg .predpred %r962;
.reg .u64 %r963;
.reg .u64u32 %r983;
.reg .pred %r984;
.reg .pred %r985;
.reg .pred %r986;
.reg .u64 %r988;
.reg .pred %r989;
.reg .u32 %r994;
.reg .pred %r995;
.reg .pred %r996;
.reg .pred %r998;
.reg .u32 %r1003;
.reg .predpredpred %r1056;
.reg .u32pred %r1065;
.reg .u64 %r1067;
.reg .pred %r1068;
.reg .u32 %r1073;
.reg .pred %r1074;
.reg .predu32pred %r1123;
.reg .pred %r1125;
.reg .u32 %r1130;
.reg .pred %r1131;
.reg .u64 %r1132;
.reg .predu32 %r1172;
.reg .u32 %r1177;
.reg .pred %r1178;
.reg .u64 %r1179;
.reg .pred %r1180;
.reg .u64pred %r1188;
.reg .u32 %r1190;
.reg .predu16 %r1214;
.reg .u32u32 %r1221;
.reg .u64 %r1229;
.reg .pred %r1231;
.reg .u64 %r1232;
.reg .u32 %r1233;
.reg .pred %r1234;
.reg .u32 %r1237;
.reg .u32 %r1238;
.reg .u64 %r1245;
.reg .u64 %r1246;
.reg .u64 %r1247;
.reg .u32 %r1248;
.reg .predu16 %r1258;
.reg .u3273 12
ld.u16 %r430,[%r413+16];
and.b16 %r429,%r430,128;
setp.eq.u16 %r431,%r429,0;
@ %r431 bra $L2;
.loc 1 873 33
ld.u64 %r432,[%r413+24];64412.loc 1 1192 13
mov.u64 %r415,%r388;
bra $L63;
$L65:.loc 1 1192 13
mov.u64 %r415movmovmovmovmov.u64 %r415,%r400;
bra $L127;
$L129:
cvt.u64.u32 %r254,%r401;
mov1003,[%value_in];
}
setp.ne.u32 %r1004,%r1003608predu16 %r612;
.reg .predpred %r629;
.reg .u64 %r632;
.reg .u64u64 %r652;
.reg .u32 %r653;
.reg .pred %r654;
.reg .u32 %r656;
.reg .u32u32u32 %r673;
.reg .pred %r676;
.reg .pred %r679;
.reg .predu32 %r699;
.reg .pred %r700;
.reg .predu32 %r713;
.reg .pred %r714;
.reg .u64pred %r754;
.reg .u64pred %r793;
.reg .u32 %r794;
.reg .predu32predu16 %r828;
.reg .u32u64 %r864;
.reg .pred %r865;
.reg .predu64 %r877;
.reg .pred %r878;
.reg .u32predpred %r951;
.reg .u64 %r953;
.reg .pred %r954;
.reg .u32 %r959;
.reg .predpred %r971;
.reg .predu32 %r1031;
.reg .u32 %r1032;
.reg .pred %r1033;
.reg .u64 %r1035;
.reg .u32 %r1036;
.reg .pred %r1037;
.reg .u32 %r1042;
.reg .pred %r1043;
.reg .pred %r1044;
.reg .predpredu64predu64 %r1108;
.reg .pred %r1109;
.reg .u32 %r1110;
.reg .pred %r1111;
.reg .u64 %r1113;
.reg .u32u32pred %r1176;
.reg .u32 %r1181;
.reg .pred %r1182;
.reg .u32 %r1183;
.reg .pred %r1184;
.reg .u64 %r1185;
.reg .u64 %r1186;
.reg .predpredpredpred %r1238;
.reg .u32 %r1243;
.reg .predpred %r1248;
.reg .u32 %r1253;
.reg .predpred %r1264;
.reg .u64 %r1267;
.reg .pred %r1268;
.reg .u64u32 %r1284;
.reg .pred %r1285;
.reg .u32 %r1288;
.reg .u32 %r1295;
.reg .u64 %r1299;
.reg .pred %r1300;
.reg .predu32.u32 %r428,[%r443];[%frame],%r428;
$L82:
.loc 1 915 10
mov.u32 %r569,0;
st.u32 [%frame+4],%r569;
.loc 1 917 9
st.u32 [%frame+392],%r569;
.loc 1 918 4.u32 %r429,[%r443];
add.u64 %r443,%r443,4;
.loc 1 921 13
and.b32 %r576,%r283,64;88;
cvt.u16.u32 %r578,%r429;
cvt.s64.s16 %r288,%r578;
.loc 1 923 8
mov.u64 %r61,%r288;
bra $L86;
$L88:
.loc 1 921 13
cvt.s64.s32 %r288,%r429;
.loc 1 923 8
mov.u64 %r61997,%r996,0;
@ %r997 bra $L173;
.loc 1 1458 7
ld.u32 %r177,[%frame+376];
.loc 1 1521 3
ld.u64 %r406,[%frame+360];
.loc 1 1457 7
mov.u64 %r291,%r1323;
$L201:
.loc 1 1458 7
add.u32 %r80,%r177,-1;
setp.le.s32 %r998,%r80,0;
@ %r998 bra $L194;
ld.u32 %r416,[%frame+352];
setp.le.s32 %r999,%r80,16;
@ ! %r99930 0 0 644 predu16 %r292;
.reg .u32u16 %r357;
.reg .u16 %r358;
.reg .u16u64 %r363;
.reg .u64 %r365;
.reg .predpred32u32predpred %r421;
.reg .u32predpredpredpredu32 %r473;
.reg .u32predu64 %r501;
.reg .u32 %r502;
.reg .u64 %r503;
.reg .u64pred %r533;
.reg .u16 %r534;
.reg .u32u32 %r543;
.reg .u32u16u16 %r563;
.reg .u16u64u64 %r593;
.reg .u64predpredpredpredu32predpred %r770;
.reg .pred %r772;
.reg .u64 %r773;
.reg .u64setp.eq.u64 %r285,%r281,0;
@ %r285 bra $L2;
ld.u32 %r286,[%r281+80];
setp.ne.u32 %r287,%r286,0;
@ %r28781ld.u32 %r266,[%r284]ld.u32 %r268,[%r284];
.loc 1 921 13
and.b32 %r445,%r111,64;
setp.eq.u32 %r446,%r445,0;
@ %r446 bra $L67;
cvt.u16.u32 %r447,%r268;
cvt.s64.s16 %r164,%r447;
.loc 1 923 8
mov.u64 %r61,%r164;
.loc 1 921 13
mov.u64 %r284,%r267;
bra $L65;
$L67:
cvt.s64.s32 %r164,%r268movmov.loc 1 1163 11movmovmov.u64 %r284,%r263;
bra $L99;
$L101:
cvt.u64.u32 %r164,%r264;
movu64predu32 %r492;
.reg .u16u64 %r498;
.reg .u32u32predu32predu32u32 %r582;
.reg .pred %r583;
.reg .u32 %r584;
.reg .u64 %r585;
.reg .f6432u16 %r612;
.reg .predu32 %r622;
.reg .u64 %r630;
.reg .u32u32 %r637;
.reg .predu16 %r648;
.reg .u16 %r649;
.reg .u32 %r650;
.reg .u16pred %r666;
.reg .u16 %r668;
.reg .u16 %r669;
.reg .u32 %r670;
.reg .predpred %r716;
.reg .u32pred %r723;
.reg .u64pred64pred32pred %r762;
.reg .u16u32 %r779;
.reg .u16 %r780;
.reg .predu16 %r786;
.reg .u16 %r788;
.reg .u32 %r790;
.reg .predu32 %r796;
.reg .u16 %r798;
.reg .u16 %r799;
.reg .u16 %r801;
.reg .u16 %r802;
.reg .u32predpredu64 %r851;
.reg .predu32 %r869;
.reg .pred %r870;
.reg .u64u32 %r879;
.reg .predpred %r894;
.reg .u64predpred %r914;
.reg .u64 %r916;
.reg .predu64u32 %r959;
.reg .pred %r960;
.reg .u32 %r965;
.reg .pred %r966;
.reg .predu64 %r988;
.reg .u64u32 %r998;
.reg .pred %r999;
.reg .u32predpredu64 %r1157;
.reg .predpredpredpred %r1203;
.reg .u64 %r1204;
.reg .predu32u16 %r1282;
.reg .u16 %r1283;
.reg .u32 %r1284;
.reg .u16 %r1285;
.reg .pred %r1286;
.reg .predpred.loc 1 1192 13
mov.u64 %r421,%r394;
bra $L67;
$L69:
cvt.s64.s32 %r259,%r395;
.loc 1 1194 8
mov.u64 %r58,%r259;
.loc 1 1192 13
mov.u64 %r421movmovmovmovmov.u64 %r421,%r406;
bra $L131;
$L133:
cvt.u64.u32 %r259,%r407;
mov1000,%r254,1;
.loc 1 1715 23
setp.ne.u32 %r1001,%r1000,0;
@ %r10011002,[%frame+176];
add.u32 %r389,%r1002200predf64u64 %r648;
.reg .u64u32 %r653;
.reg .predu32predu32u16predu32pred %r772;
.reg .u64 %r773;
.reg .u64 %r774;
.reg .u32 %r775;
.reg .pred %r776;
.reg .u64 %r777;
.reg .u64predpredpred %r803;
.reg .u64u64 %r833;
.reg .u32 %r834;
.reg .u64 %r836;
.reg .u32 %r837;
.reg .pred %r838;
.reg .u32 %r839;
.reg .pred %r840;
.reg .u32 %r841;
.reg .pred %r842;
.reg .u16u32 %r845;
.reg .pred %r846;
.reg .u32 %r847;
.reg .pred %r848;
.reg .u32 %r849;
.reg .pred %r850;
.reg .u16u32 %r876;
.reg .u32u32u32 %r903;
.reg .pred %r906;
.reg .u64 %r908;
.reg .u64 %r910;
.reg .u64u32 %r954;
.reg .predu64 %r977;
.reg .pred %r978;
.reg .u32 %r983;
.reg .predpredu64 %r1008;
.reg .pred64predpredpred %r1088;
.reg .u64 %r1090;
.reg .u32u64u32predpred %r1199;
.reg .u32 %r1204;
.reg .pred %r1205;
.reg .predpred %r1248;
.reg .pred %r1249;
.reg .pred %r1250;
.reg .u64 %r1252;
.reg .pred %r1253;
.reg .u32 %r1258;
.reg .predpred %r1271;
.reg .u32 %r1276;
.reg .pred %r1277;
.reg .u64 %r1279;
.reg .pred %r1280;
.reg .u32 %r1285;
.reg .pred %r1286;
.reg .u32 %r1287;
.reg .predu32 %r1308;
.reg .pred %r1309;
.reg .u32 %r1310;
.reg .pred %r1311;
.reg .u32 %r1312;
.reg .pred %r1313;
.reg .u32 %r1318;
.reg .pred %r1319;
.reg .u64 %r1322;
.reg .pred %r1323;
.reg .u64 %r1327;
.reg .u32 %r1328;
.reg .pred %r1330;
.reg .u16 %r1333;
.reg .u16 %r1334;
.reg .pred %r1335;
.reg .u64 %r1338;
.reg .u32 %r1339;
.reg .pred %r1340;
.reg .u32 %r1343;
.reg .u32 %r1350;
.reg .u64 %r1354;
.reg .pred %r1355;
.reg .pred %r1356;
.reg .pred %r1357;
.reg .pred %r1358;
.reg .u32 %r1360;
.reg .u32mov.u64 %r455,%ar0;
mov.u64 %r456,%ar1;
mov.u64 %r457,%ar2;
mov.u64 %r458,%ar3;
.loc 1 424 6
mov.u32 %r460,0;
st.u32 [%frame+12881300],%r464;
.loc 1 591 2
setp.eq.u64 %r465,%r455,0;
@ %r465 bra $L25;
ld.u32 %r466,[%r455+80];25r45.u32 %r443,[%r458];[%frame],%r443;
$L88:
.loc 1 915 10
mov.u32 %r624,0;
st.u32 [%frame+4],%r624;
.loc 1 917 9
st.u32 [%frame+1304],%r624;
.loc 1 918 4.u32 %r444,[%r458];
add.u64 %r458,%r458,4;
.loc 1 921 13
and.b32 %r631,%r287,6494;
cvt.u16.u32 %r633,%r444;
cvt.s64.s16 %r294,%r633;
.loc 1 923 8
mov.u64 %r64,%r294;
bra $L92;
$L94:
.loc 1 921 13
cvt.s64.s32 %r294,%r444;
.loc 1 923 8
mov.u64 %r64.loc 1 356 3